With continuous transistor scaling, gate-to-drain (source) capacitance increases due to the increased proximity of the source/drain metallization contacts (vias) to the gate conductor. For instance, the distance between the contact via and the gate conductor can be as low as 40 nm in dense logic circuits such as fast static random access memory (SRAM) cells in 65 nm technology. With misalignment of the contact via with respect to the gate, the spacing between the gate and the via can be significantly less than 40 nm. To make matters worse, due to Miller effect the capacitance between the gate and drain via is multiplied by the gain of the CMOS stage.
As a result, the total gate-to-drain/source capacitance becomes a significant portion of the overall load capacitance for fast, lightly loaded CMOS circuits with transistors fabricated in 65 nm technology and below. By reducing the total gate-to-drain capacitance, significant leverage in increasing circuit speed can be realized.
Other advantages of inherently reduced gate Miller capacitance include a higher stability for memory cells (due to less charge coupling) and a higher packaging density.
In view of the above, there is still a need for providing a CMOS structure in which the gate-to-drain/source capacitance is reduced.